//------------------------------------------------------------
//  Filename: fusion_top.v
//   
//  Author  : wlduan@gmail.com
//  Revise  : 2016-09-26 12:41
//  Description: 
//   
//  Copyright (C) 2014, YRBD, Inc.                           
//  All Rights Reserved.                                       
//-------------------------------------------------------------
//
`timescale 1ns/1ps
 
module FUSION_TOP  #(
    parameter integer C_S_AXI_DATA_WIDTH     = 32,
    parameter integer C_S_AXI_ADDR_WIDTH     = 16,
    parameter integer C_M_AXI_BURST_LEN      = 64,
    parameter integer C_M_AXI_ID_WIDTH       = 1,
    parameter integer C_M_AXI_ADDR_WIDTH     = 32,
    parameter integer C_M_AXI_DATA_WIDTH     = 32,
    parameter integer C_M_AXI_AWUSER_WIDTH   = 0,
    parameter integer C_M_AXI_WUSER_WIDTH    = 0,
    parameter integer C_M_AXI_BUSER_WIDTH    = 0    
) ( 
    input  wire                                 REGS_AXI_ACLK,
    input  wire                                 REGS_AXI_ARESETN,
    input  wire [C_S_AXI_ADDR_WIDTH-1 : 0     ] REGS_AXI_AWADDR,
    input  wire                                 REGS_AXI_AWVALID,
    output wire                                 REGS_AXI_AWREADY,
    input  wire [C_S_AXI_DATA_WIDTH-1 : 0     ] REGS_AXI_WDATA,
    input  wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0 ] REGS_AXI_WSTRB,
    input  wire                                 REGS_AXI_WVALID,
    output wire                                 REGS_AXI_WREADY,
    output wire [1 : 0                        ] REGS_AXI_BRESP,
    output wire                                 REGS_AXI_BVALID,
    input  wire                                 REGS_AXI_BREADY,
    input  wire [C_S_AXI_ADDR_WIDTH-1 : 0     ] REGS_AXI_ARADDR,
    input  wire                                 REGS_AXI_ARVALID,
    output wire                                 REGS_AXI_ARREADY,
    output wire [C_S_AXI_DATA_WIDTH-1 : 0     ] REGS_AXI_RDATA,
    output wire [1 : 0                        ] REGS_AXI_RRESP,
    output wire                                 REGS_AXI_RVALID,
    input  wire                                 REGS_AXI_RREADY,  
     
    //************* Read channel ***********  
    input  wire                                 VGA_AXI_ACLK,
    input  wire                                 VGA_AXI_ARESETN,   
    output wire [C_M_AXI_ADDR_WIDTH-1 : 0     ] VGA_AXI_ARADDR,
    output wire [7 : 0                        ] VGA_AXI_ARLEN,
    output wire [2 : 0                        ] VGA_AXI_ARSIZE,
    output wire [1 : 0                        ] VGA_AXI_ARBURST,
    output wire [3 : 0                        ] VGA_AXI_ARCACHE,
    output wire                                 VGA_AXI_ARVALID,
    input  wire                                 VGA_AXI_ARREADY,
    output wire [2 : 0                        ] VGA_AXI_ARPROT,
    input  wire [C_M_AXI_DATA_WIDTH-1 : 0     ] VGA_AXI_RDATA,
    input  wire [1 : 0                        ] VGA_AXI_RRESP,
    input  wire                                 VGA_AXI_RLAST,
    input  wire                                 VGA_AXI_RVALID,
    output wire                                 VGA_AXI_RREADY,
    //************* Write channel ***********
    input  wire                                 CAMERA_AXI_ACLK,
    input  wire                                 CAMERA_AXI_ARESETN,
    output wire [C_M_AXI_ID_WIDTH-1 : 0       ] CAMERA_AXI_AWID,
    output wire [C_M_AXI_ADDR_WIDTH-1 : 0     ] CAMERA_AXI_AWADDR,
    output wire [7 : 0                        ] CAMERA_AXI_AWLEN,
    output wire [2 : 0                        ] CAMERA_AXI_AWSIZE,
    output wire [1 : 0                        ] CAMERA_AXI_AWBURST,
    output wire                                 CAMERA_AXI_AWLOCK,
    output wire [2 : 0                        ] CAMERA_AXI_AWPROT,
    output wire [3 : 0                        ] CAMERA_AXI_AWCACHE,
    output wire [3 : 0                        ] CAMERA_AXI_AWQOS,
    output wire [C_M_AXI_AWUSER_WIDTH-1 : 0   ] CAMERA_AXI_AWUSER,
    output wire                                 CAMERA_AXI_AWVALID,
    input  wire                                 CAMERA_AXI_AWREADY,
    output wire [C_M_AXI_DATA_WIDTH-1 : 0     ] CAMERA_AXI_WDATA,
    output wire [C_M_AXI_DATA_WIDTH/8-1 : 0   ] CAMERA_AXI_WSTRB,
    output wire                                 CAMERA_AXI_WLAST,
    output wire [C_M_AXI_WUSER_WIDTH-1 : 0    ] CAMERA_AXI_WUSER,
    output wire                                 CAMERA_AXI_WVALID,
    input  wire                                 CAMERA_AXI_WREADY,
    input  wire [C_M_AXI_ID_WIDTH-1 : 0       ] CAMERA_AXI_BID,
    input  wire [1 : 0                        ] CAMERA_AXI_BRESP,
    input  wire [C_M_AXI_BUSER_WIDTH-1 : 0    ] CAMERA_AXI_BUSER,
    input  wire                                 CAMERA_AXI_BVALID,
    output wire                                 CAMERA_AXI_BREADY,
    //-------------------------------------------------------- 
    input  wire                                 clk_7x_vga,
    input  wire [15:0]                          key_in,
    output wire                                 key_intr,

    output wire                                 rtc_scl,
    inout  wire                                 rtc_sda,

    output wire                                 eeprom_scl,
    inout  wire                                 eeprom_sda,

    output wire                                 adc_scl,
    inout  wire                                 adc_sda,

    output wire                                 dac_sclk,
    output wire                                 dac_sdata,
    output wire                                 dac_load,
    output wire                                 gaoya,
    //-------------------------------------------------------- 
    output wire                                 camerax_pwrdown,
    output wire                                 camerax_resetn,

    input  wire                                 camera0_pclk, 
    input  wire [7:0]                           camera0_yuv , 
    input  wire                                 camera0_h_sync, 
    input  wire                                 camera0_v_sync, 
    output wire                                 camera0_sclk,
    inout  wire                                 camera0_sda ,

    input  wire                                 camera1_pclk, 
    input  wire [7:0]                           camera1_yuv , 
    input  wire                                 camera1_h_sync, 
    input  wire                                 camera1_v_sync, 
    output wire                                 camera1_sclk,
    inout  wire                                 camera1_sda ,
    //--------------------------------------------------------
    output wire                                 txout0_p,
    output wire                                 txout0_n,
    output wire                                 txout1_p,
    output wire                                 txout1_n,
    output wire                                 txout2_p,
    output wire                                 txout2_n,
    output wire                                 txout3_p,
    output wire                                 txout3_n,
    output wire                                 txclk_p,
    output wire                                 txclk_n
);      
 

endmodule
